Communication of multi-bit data from a source to a receiver may be performed by converting the multi-bit data into a serial bit stream, transmitting the serial bit stream to the receiver, and then at the receiver converting the serial bit stream back into multi-bit data. Reasons for communicating multi-bit data as a serial bit stream, as opposed to transmitting its multiple bits concurrently over a multi-line bus, include limitations on bus width.
Converting an N-bit multi-bit data into a serial bit stream typically begins by clocking all N-bits together, broadside, into a parallel-in-serial-out shift register and then applying N clocks of a serializer clock SCK to shift the N-bits out through a serial output as N consecutive bits. If the N-bit data rate is substantially continuous at FS N-bit words per second, then the rate of the serial bit stream, in bits per second (BPS) must equal N multiplied by FS. The serializer clock SCK frequency must therefore be the same as that BPS.
In conventional serial bit stream communications the receiver must either receive the serializer clock SCK with the bit stream or locally generate the same SCK used. By the serializer/transmitter, frequency and phase locked to the bit stream, Local generation of the SCK requires the receiver have substantially the same high speed clock generating capability as the serializer/transmitter and, in certain applications, this may be less than optimal. Such applications may therefore require the serializer/transmitter transmit the serializer clock SCK to the receiver. There are two means to perform the transmission. The first is to embed SCK in the serial bit stream signal, from which the receiver may recover SCK. However, for reasons known to persons of ordinary skill in the art, in certain applications communication using an embedded clock signal may be not optimal. The second means for communicating SCK from the serializer/transmitter to the receiver is by a separate transmission line.
The related art FIG. 1 shows such a conventional separate clock line communication system 100. The communication system 100 includes a conventional serializer/transmitter 102 having n serializer 103 for converting multi-bit data to a serial bit stream, a conventional receiver 104, and two lines extending from the former to the latter, one being a serial bit transmission line 106, the other being the separate SCK, clock transmission line 108 for the serializer SCK generated by the SCK generator 109. In addition, the conventional serializer/transmitter 102 includes a clock line driver 110, and the conventional receiver 104 includes a clock receiving buffer 112. In operation the conventional serializer/transmitter 102 clock line driver 110 drives the clock transmission line 108 with SCK, the conventional receiver 104 receives the transmitted SCK, adjusts the phase through a phase rotator 114 to obtain optimal sampling, and uses it to clock the phase shifted sampler 116.
Such conventional means as depicted by the related art FIG. 1 for serializing N-bit data into a bit stream, communicating the bit stream and the serializing clock, recovering the serial bits and re-converting these recovered serial bits to parallel N-bit data, has various shortcomings One example shortcoming is the power required for its serializer/transmitter 102 to forward the serializing clock to the receiver 104. The total of this power consumed in forwarding SCK signal includes the power draw of the clock line driver (e.g., 110) within the serializer/transmitter 102 and the power draw of the clock receiving buffer (e.g., 112) in the receiver 104.